The present invention relates to a semiconductor integrated circuit and, particularly, to a protection circuit for protecting a semiconductor integrated circuit against overvoltage applied to a source terminal or ground terminal thereof due to electrostatic charge.
In a CMOS integrated circuit of twin-well type, a P well and an N well are provided in a surface portion of, for example, a P type silicon substrate. An N channel MOS FET is formed in the P well and a P channel MOS FET is formed in the N well. A P.sup.+ diffusion layer (substrate contact region) selectively formed in a surface portion of the P well and a source region of the N channel MOS FET are connected to a ground terminal through a first metal film such as an aluminum film. Similarly, an N.sup.+ diffusion layer (well contact region) formed selectively in a surface portion of the N well and a source region of the P channel MOS FET are connected to the ground terminal through another first metal film.
When a positive overvoltage is applied to a source terminal thereof, current flows from the well contact region and the source region of the P channel MOS FET to the ground terminal through the N well, the P well (assuming that the N and P wells are in contact with each other), the substrate contact region and the source region of the N channel MOS FET.
That is, discharge occurs due to breakdown of a PN junction formed by the N well and the P well. The breakdown voltage is usually about 70 volts.
When a positive overvoltage is applied to the ground terminal, current flows through the substrate contact region, the P well, the N well and the well contact region to the source terminal.
Thus, the CMOS circuit itself has a certain protective function. However, the breakdown voltage of a diode formed between the aforementioned wells is so high that it is necessary to provide a specific protection circuit if the thickness of a gate oxide film is small.
There are various schemes in such a protection circuit. Among them, a protection circuit using field effect transistors is practical since it can be realized without adding any new step to a fabrication process for the semiconductor integrated circuit. This protection circuit is disclosed in Japanese Laid-Open (Kokai) patent application 60-10767. In this Kokai, a parallel circuit of first and second field effect transistors which are MOS FETs having field oxide films as their gate oxide films, respectively, are inserted between a power source source wiring and a ground wiring, a gate electrode of the first field effect transistor is connected to the power source source wiring and a gate electrode of the second field effect transistor is connected to the ground terminal.
When a positive overvoltage exceeding a threshold voltage of the first field effect transistor is applied to the power source source terminal, the first field effect transistor is turned on to allow current to flow to the ground wiring. Although, when a positive overvoltage is applied to the ground terminal, the second field effect transistor does not operate as a MOS FET (since its gate electrode and the substrate are connected to the ground wiring), current flows to the power source source wiring through a PN junction between regions of the substrate-source/drain regions which are connected to the power source wiring.
Electrostatic discharge upon which such positive overvoltage is applied to the power source terminal takes the form of channel current of the first field effect transistor. However, the resistance of the MOS FET when in the conduction state may be at least several times that of a bipolar transistor. When the thickness of a gate oxide film of a MOS FET of an internal circuit is 10 to 20 nm, the channel width of the first field effect transistor should be about 2000 .mu.m. Thus, the protection circuit comprising field effect transistors has a low electrostatic discharge ability which affects integration density.